Devices fabricated using silicon-on-insulator (SOI) substrates provide certain performance improvements, such as lower parasitic junction capacitance, in comparison with comparable devices built directly in a bulk silicon substrate. Generally, SOI substrates include a thin active layer of silicon partitioned into discrete electrically-isolated device regions for devices and a thin buried layer of an insulator, such as silicon dioxide (SiO2), electrically isolating the active layer from the rest of the substrate. Traditional field effect transistors (FETs) feature source and drain regions formed within the active layer of the SOI substrate, a channel region in the active layer that is disposed between the source and drain regions, and a gate overlying the channel region. A voltage applied to the gate regulates the current flowing from the source region through the channel region to the drain region.
Complementary metal-oxide-semiconductor (CMOS) circuits include n-channel field effect transistors (nFETs), in which electron carriers are responsible for conduction in the channel region, and p-channel field effect transistors (pFETs), in which hole carriers are responsible for conduction in the channel region. CMOS circuits are typically fabricated on silicon wafers having a single crystal orientation, ordinarily a (100) crystal orientation. Electrons have a higher mobility in silicon characterized by a (100) crystal orientation in comparison with a (110) crystal orientation. In contrast, holes have higher mobility in silicon characterized by a (110) crystal orientation in comparison with a (100) crystal orientation.
In recognition of this ability to optimize device performance, hybrid orientation technology (HOT) has evolved to produce hybrid SOI substrates characterized by device regions of different crystal orientations. CMOS circuits can be fabricated using such hybrid SOI substrates with nFETs formed in silicon device regions of a (100) crystal orientation and pFETs formed in silicon device regions of a (110) crystal orientation. Consequently, the device performance of each device type in the CMOS circuit can be individually optimized.
Despite the development of such hybrid SOI substrates, improved design structures are needed to further optimize the performance of CMOS circuits including nFETs and pFETs carried by hybrid SOI substrates.